It is well known that lateral dimensions of n-channel metal oxide semiconductor (NMOS) and p-channel metal oxide semiconductor (PMOS) transistors in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) are shrinking in time with each new fabrication technology node, as articulated by Moore's Law. P-type source and drain (PSD) regions in PMOS transistors are typically formed by ion implanting dopants and other species, producing end of range defects which cause undesirable leakage current; the relative detrimental impact of end of range defects increases as transistor size shrinks. Laser annealing, flash annealing and other ultra high temperature (UHT) processes which heat surfaces of ICs over 1200 C for time periods less than 100 milliseconds, when performed before other anneal processes, have demonstrated significant reductions of end of range defects. Rapid thermal processing (RTP) methods, such as spike anneals, which heat ICs for time periods longer than 1 second, are not as effective at reducing end of range defects due to the necessarily lower temperatures used. Increasing temperatures above 1200 C in a rapid thermal anneal process to annihilate end of range defects would produce unacceptably high spreads in spatial distributions of boron dopants in the PSD regions. Boron has a higher diffusivity than commonly used n-type dopants, so typical CMOS IC fabrication process sequences form n-type source and drain (NSD) regions in NMOS transistors before PSD regions to minimize the thermal profile on the implanted dopants in the PSD regions.
NMOS transistors in advanced CMOS ICs are frequently enhanced by a process sequence known as stress memorization technique (SMT), in which a layer of tensile material is deposited on an IC after the NSD ion implantation process is performed and before a subsequent anneal process. During the anneal, the polycrystalline silicon (polysilicon) in the NMOS gate, which was partially amorphized by the NSD ion implants, recrystallizes with a grain configuration that exerts stress on the underlying NMOS channel when the tensile material layer is removed. The resultant strain in the NMOS channel increases the mobility of charge carriers, which desirably improves the on-state current. UHT processes are incompatible with SMT processes for several reasons: UHT annealing before deposition of the tensile layer causes recrystallization of the polysilicon in the NMOS gate, greatly reducing the SMT effect, while UHT annealing after deposition of the SMT layer hardens the SMT layer to the point of making removal problematic.